This invention relates, in general, to non-saturating bipolar transistor circuits, and more particularly to translator circuits for converting ECL levels to CMOS levels.
It is well known that a bipolar transistor driven into saturation greatly increases the time needed to turn the device off. Saturation is defined by both collector-base and base-emitter junctions of a bipolar transistor being forward biased. Circuits having bipolar transistors which operate in deep saturation may have increased delays that are unacceptable for many applications.
One application that is prone to deep saturation is an output stage that operates near the power supply voltages. As an example, an ECL (emitter coupled logic) to CMOS (complementary metal oxide semiconductor) level translator operates near its supply voltages. A CMOS one logic level is at the positive most potential of the circuit while a CMOS zero logic level is at the most negative potential of the circuit (typically ground). Because CMOS logic levels are at the supply voltages of the translator circuit it is difficult not to deeply saturate transistors generating these signal levels.
One well known method for preventing a bipolar transistor from saturating is to couple a Schottky diode from base to collector of the bipolar transistor. The Schottky diode has a lower turn on voltage than a standard base-collector junction, thus it is enabled before the bipolar transistor saturates. The enabled Schottky diode removes base drive from the bipolar transistor keeping it from deep saturation. The one drawback to using the Schottky diode is that it takes extra processing steps to form the device and is not available on every bipolar process flow.
It would be of great benefit if a non-saturating bipolar transistor circuit could be provided that can be implemented on a standard bipolar process flow without additional processing steps.